Machine learning, quantum computing speed ahead

By Rich Kwan|December 2016

The Computer Systems Technical Committee works on advancing the application of computing to aerospace programs.

China maintained a comfortable lead in high-performance computing. Sunway TaihuLight, a supercomputer at China’s National Supercomputing Center near Shanghai, was the leader in the June edition of the Top 500 list with 93.0 petaflops. TaihuLight is composed of 10,649,600 computing cores in 40,960 nodes. Designed and manufactured in China, each node is a ShenWei SW26010 chip, with 256 slave compute cores and four management cores, giving a total of 260 cores per chip. TaihuLight displaces the previous champion, Tienhe-2 (Milky Way 2), which performs at 33.9 petaflops, and is built of Intel Xeon processors. In third place is Titan, at Oak Ridge National Lab, running at 17.6 petaflops.

Google’s research into machine learning is now integrated in some of its products, including speech recognition, Google Photos, Gmail and search. In late 2015, the company released “TensorFlow,” an open source library for software neural networks, thus doing intense numerical computation on clusters of central processing units and graphics processing units. In May, Google announced a hardware enhancement. The Tensor Processing Unit, or TPU, is a custom chip built for machine learning — particularly for TensorFlow. TPUs had been at work in Google’s data centers for over a year and were giving an order of magnitude better performance per watt for machine learning than GPUs, not to mention CPUs.

For a wide range of optimization problems, quantum computing may prove even faster. Google, NASA’s Ames Research Center in California and Universities Space Research Association, based in Washington, D.C., are cooperating in the Quantum Artificial Intelligence Laboratory at Ames. The QuAIL project has a D-Wave 2X, with more than 1,000 quantum bits. In a paper published in January, Google researchers reported quantum annealing that ran many orders of magnitude faster than simulated annealing on a conventional single core machine.

The Juno spacecraft entered a highly elliptical orbit around Jupiter on July 4 and will make multiple passes through Jupiter’s radiation belts. The mission design prompted the construction of an “electronics vault,” essentially a titanium box, to shield the avionics, including its BAE Systems RAD750 computer, from the more extreme effects of the radiation.

The mobile processors found in devices like smartphones and tablets are fueling competition for mass market consumption of small unmanned aircraft. DJI, of Shenzhen, China, released an embedded computer based on Nvidia’s Tegra TK1 as a developer platform for its popular line of camera-carrying drones in November last year. In January, Intel announced it had acquired German drone maker Ascending Technologies. At the Consumer Electronics Show that month, the company showed a video of “Drone 100,” a swarm of 100 drones performing an airborne music and light show. The drones gave a live performance in June at Australia’s Sydney Opera House and were accompanied by the Sydney Youth Orchestra.

NASA’s Goddard Space Flight Center in Maryland issued a request for proposal in June for the High Performance Spaceflight Computing Processor Chiplet project. It aims to develop a next-generation, radiation-hardened, general-purpose, multicore processor for use by NASA and the U.S. Air Force for crewed and uncrewed spacecraft. As currently envisioned, the four-year project would deliver a quad-core, radiation-hardened version of the ARM Cortex-A53, including the single-instruction, multiple-data Neon extension.

Meanwhile, BAE has received the first silicon for its RAD5545 system on a chip, a quad-core implementation of the RAD5500 32/64-bit Power Architecture. It has over 19 times the performance of the RAD750 on Juno. Maximum processor throughput is 5.6 billion operations per second or 3.7 billion floating point operations per second. It is built using a radiation-hardened-by-design circuit library using a 45-nanometer silicon-on-insulator fabrication process. It is designed to work with the SpaceVPX standard, supporting RapidIO and SpaceWire hardware protocols. ★

Contributor: Joe Marshall