Information Systems

Ensuring security while building faster supercomputers

The Computer Systems Technical Committee works on advancing the application of computing to aerospace programs.

Whether or not semiconductor technology has reached the limits of Moore’s law, the way forward in computing is massive, highly orchestrated parallelism. On the ground, it enables researchers to push the boundaries of energy, advanced materials, artificial intelligence, biology and more. In flight, it enables vehicle or payload autonomy, with increased awareness of surroundings and better real-time decision-making. However, designers need to be careful that clever advances in performance don’t result in architectural holes that can breach security, as was reported this year.

In June, the U.S. Department of Energy’s Oak Ridge National Laboratory in Tennessee unveiled the Summit supercomputer as the world’s most powerful and smartest scientific supercomputer. It immediately led the Top500 supercomputer list with a High Performance Linpack, or HPL, rating of 122.3 petaflops (thousand million million floating point operations per second). For certain scientific applications, it will exceed 3.3 exaops (billion billion mixed precision calculations per second). Summit is composed of 4,608 compute nodes, each with two 22-core IBM Power9 processors and six NVIDIA Tesla V100 graphic processing units, or GPUs. Each Tesla V100 has 5,120 CUDA GPU cores and 640 Tensor matrix-processing cores.

The prior top supercomputer, Sunway TaihuLight, developed by China’s National Research Center of Parallel Computer Engineering and Technology, became No. 2 on the Top500 list, with an HPL rating of 93 petaflops. No. 3 was Sierra at the Department of Energy’s Lawrence Livermore National Lab. It delivered 71.6 petaflops on HPL. Its architecture is similar to Summit; it has 4,320 compute notes, each with two IBM Power9 CPUs plus four NVIDIA Tesla V100 GPUs.

Advanced mobile systems require a mixture of sensor, computing and radio frequency technologies and are limited by size, weight and power. These typically use different types of semiconductors, e.g., gallium arsenide, complementary metal-oxide semiconductor or p-doped MOS. DARPA is trying to bring together existing designs in these different technologies through its CHIPS program, short for Common Heterogeneous Integration and Intellectual Property Reuse Strategies. Rather than fabricating a chip in a single technology, CHIPS intends to integrate chiplets from different technologies into a single physical package.

A major hurdle in the CHIPS program is interconnection between the different chiplets. At the DARPA Electronics Resurgence Initiative Summit in July, Intel announced it would provide a royalty-free license to its Advanced Interface Bus to CHIPS participants and others. The company is already applying this with its 8th Gen Intel Core, Radeon Graphics and Stratix field-programmable gate array.

The summit also introduced a couple of projects aimed at realizing a 24-hour design for defense-related hardware. One, known as the Intelligent Design of Electronic Assets program, aims for a “no human in the loop” layout generator to be developed by Cadence and several partners. Another, known as POSH Open Source Hardware, aims to help democratize access to custom, high performance systems on chips through open-source IP.

The microarchitecture of high performance processors came under attack this year, causing microprocessor vendors to issue urgent patches and redesign parts of chips due out later this year. In January, exploits Spectre and Meltdown were reported; variants followed in later months. The exploits affect several generations of products and affect the “speculative execution” pipeline in computers ranging from servers to smartphones. One way to stop them is to turn off out-of-order execution; but this dramatically impacts performance.

Simpler processors like microcontrollers, which typically talk to sensors and controllers, are largely unaffected. Similarly, advanced GPUs used for machine learning get their speed from many identical compute cores rather than heavy pipelining. Conversely, functions such as object identification and vehicle autonomy utilize the types of processor currently affected.

Photo: The Summit supercomputer at Oak Ridge National Laboratory in Tennessee is the world’s most powerful scientific computer. Credit: Oak Ridge National Laboratory/Carlos Jones

Ensuring security while building faster supercomputers